Et XC6slx25T, N3csg324i Spartan-VI FPGA habet usque ad sex Cmts, inter se constans duos DCMs et unum PLL, et potest esse soli vel in cascade. Et Spartan-VI FPGA extendit ad densitatem MMMDCCCXL ad (CXLVII) CDXLIII logica unitates, cum tantum dimidium potentia consummatio de prior Spartan series, et habet citius et magis comprehendo coniunctivity. Et Spartan-VI seriem adoptat perfectum XLV nanometer humilis-potentia aeris processus technology, achieving optimum statera ex sumptus, virtute consummatio, et perficientur, initus novus et magis agentibus et dives initus, in cuneos, et inputat.
XCZU9CG, L1FFVB1156I Hoc productum integrates a pluma dives LXIV frenum quad Core vel Dual Core Armem ® Cortex ® - A53 et Dual Core brachium Cortex-R5F Processing System (Ex Xilinx) ® UltraScale? MPSoc architectura. Insuper etiam includit in-chip memoria, multi Portus externum Memoria interfaces et varietate periphericis connexa interfaces.
In Xcku060-2ffva1156i agro programmable porta ordinata potest consequi maxime princeps signum processus Sed in medium-range cogitationes et altera-generation Transceolvivers. FPGA est semiiconductor fabrica fundatur in configurable logica obstructionum (CLB) vulvam coniuncta per programmable internonnect ratio
In 10m50daf484c8g fabrica est una chip, non-volatile-cost programmable logica fabrica (PL) ad integrate optimum set ratio components.
Xczu47dr-2ffve1156i embedded ratio in chip (Soc) est unum-chip adaptive RF platform quod potest occursum current et futurum industria necessitates. Et Zynq ultrasscale + Rfsoc series potest sustinere omnes frequency vincula infra 6GHz, occurrens in discrimine requisitis proximo-generation 5g deployment. In eodem tempore, quod potest etiam auxilium directe sampling pro XIV frenum Analog-ut-digital converters (ADCs) cum sampling rate of usque ad 5GS / s et XIV frenum in-to-X GS / s, et de quibus est analog et ad 6GHz.
In 10Ataf115R3F40I2LG est summum faciendo medium-range XX Nanometer FPGA cum XCVI Full Duplex Transceivers, Supporting a chip ad chip data rate of 17.4gbps. In addition, in FPGA quoque praebet a backplane data serie rate of usque ad 12,5 Gbps et usque ad 1.15 million equivalent logicam unitates.
